Embedded vector processor is an effective way to implement software radio

One of the reasons for the market success of dedicated wireless transceiver modules such as Bluetooth and Wi-Fi is that most of these communication modules are additional functions, not standard configurations. Therefore, those that allow manufacturers to configure solutions that support different standard devices by simply plugging in the appropriate modules, including the necessary RF and baseband processing parts, have significant benefits.

However, as these wireless communication channels gradually become standard equipment, the continued use of such a dedicated module has great problems. Not only the total volume of each module is difficult to accommodate, the total power consumption will also greatly shorten the battery life, and the increase in silicon area will have a negative impact on the production cost. In addition, in the case where multiple communication channels must be activated simultaneously, coexistence of multiple modules will be problematic because mutual interference occurs between the antennas.

Multiple communication channels

Reducing the size, cost, power consumption, and antenna interference means that a special architecture is needed in which all or part of the radio and baseband functions will be shared to different radio communication channels. For example, in an integrated solution, multiple channels operating in the same frequency band (such as Bluetooth and IEEE 802.11b/g) can intelligently share radio frequency hardware such as antennas, low noise amplifiers, and mixers. Likewise, channels using similar modulation schemes can share a single programmable modem.

In this way, a new multi-band multi-mode architecture is formed, in which different RF parts and different modems are integrated, and it is better to have a standardized digital interface with each other. In order for a single hardware modem to serve multiple different wireless communication channels, a highly flexible, software programmable modem engine is required.

Figure 1: Schematic diagram of module mapping on communication pipeline and internal hardware proposed by NXP

In fact, the modem engine is one of the best entry points for manufacturers to achieve product differentiation in the market, because these engines can be used to enhance wireless performance. The air interface of any mobile communication standard has a strict definition. In addition to selecting the best implementation technology (such as using appropriate RF CMOS, BiCOMS, or GaAs process technology), manufacturers have difficulty in enhancing the space of the RF front-end performance. The type of algorithm required for the implementation of the codec at the other end of the modem pipeline is well defined. The modem located between the RF front-end and the codec is very important. Here, the proprietary IP can be used to process the modulated/demodulated signal first and then sent to the codec to obtain a lower value. Bit error rate (BER), or lower transmit/receive power at certain BER conditions.

Since the above signal processing and adjustment must adapt to local conditions, such as multipath fading and interference, it is ideal to accomplish this task by a DSP algorithm running on a high-end software programmable DSP. This programmable approach can adapt to changing standards and field test results, and it can add new, more intelligent algorithms (eg, to improve signal-to-noise ratio), which is difficult in hardware solutions without going through silicon in subsequent processes. Tablet redesign can be achieved.

Given the complexity of these algorithms, processors used in modem pipeline applications must have superior performance, typically exceeding 10, 000 operations per second (Gops). However, the devices that use these designs are typically battery-powered mobile devices, which means that these processors must consume very little power (typically no more than a few hundred milliwatts). The use of advanced low power/low leakage current CMOS fabrication technology will limit the processor's maximum clock rate to 300MHz. In order to achieve the required Gops performance at this clock rate, the processor must use a very high level of parallelism (such as by performing vector-wide processing).

Algorithms that can be vectorized to operate on vector processors include signal conditioning functions such as equalization, interference cancellation and multipath correlation (Rake receivers), and signal processing functions such as synchronous, quadrature amplitude modulation (QAM) mapping/ De-mapping and FFT for OFDM demodulation.

Software programmable features of course have other advantages. It allows OEMs to differentiate their products using a single, free silicon platform. It will help upgrade to more advanced algorithms in the future. DSP-based modems also perform more flexibly when upgrading modem performance or adding performance during the design process. What are the alternatives to programmable architecture? There are currently two other methods that can be used: hard-wired dedicated building blocks and reprogrammable/reconfigurable hardware such as FPGAs.

Hard-wired building blocks are currently used primarily for handsets that implement only a relatively small (fixed) number of standards. Although they are extremely cost-effective for these limited applications, their required area increases dramatically as the number of standards increases. In fact, recent NXP analysis of currently available solutions shows that the use of a dedicated module approach to process Edge, R’99, HSDPA, and HSUPA standard solutions in a single device requires more area than a programmable solution ( Such as the NXP EVP scheme) is 50% to 120% larger. The main reason is that there are big differences between different standards, and using hardware solutions to achieve efficient resource sharing between standards requires too much development time to optimize to this level. Programmable solutions also allow the addition of new, smarter algorithms without requiring new tapeouts while adapting to changing standards and field test results.

Other common solutions are to use programmable/reconfigurable hardware such as FPGA (which is a typical solution for 3G base stations). Although the level of resource reuse here is even higher than that of programmable solutions, current FPGAs are still relatively expensive in terms of silicon area, because their effective gate area is much smaller than fixed implementations (dedicated hardware or programmable architecture). . In addition, a large area will directly affect the standby time of the mobile phone, which means that leakage current may be a problem.

So from the perspective of area/cost, programmable architecture is the best solution. The power consumption of the programmable architecture is slightly higher than that of the hardwired solution, but from a larger system perspective, this trade-off is acceptable because the increased power consumption can be compensated elsewhere. For example, in the system study, NXP found that the standby power is reduced because the programmable method can implement a more intelligent algorithm to shorten the activation time in standby.

Software Radio

When implementing SDR, the "vector processor" is recommended as an extension of the classic SIMD processing type. Adding "Vector internal processing" can realize the interaction between the elements inside the vector. In this way, the data in the vector can be arbitrarily re-ordered when required for FFT butterfly operation, pilot channel deletion, and other operations that are common in communication signal processing.

Compared with pure SIMD, this method can significantly improve the computational efficiency. In this case, if the pure SIMD method is used, the sequential operation of inefficient operation is usually the only available solution. Because programmable EVP can implement highly adaptive modem functions for many different communication standards and can negotiate a smooth transition from one standard to another, programmable EVP is a key implementation unit for software radios.

In addition to meeting very high Gops conditions, this processor also meets silicon area and cost requirements for battery-powered, portable products. Its very high level of programmability not only accommodates the diversity of wireless communication systems in mobile devices, but also allows manufacturers to follow the development and usage scenarios of these standards as well as the development of new algorithms. Programmable EVP can also help manufacturers “fix” or upgrade their products “on the air” and reduce on-site repair rates or enhance the user experience by deploying wider coverage or higher data download rates.

However, the software-programmable nature of vector processors can only work when and where it provides real value in reducing time to market, increasing product differentiation, or reducing costs. In fact, there are still quite a few baseband processing occasions that are not suitable for software programming, while hardwired, more specialized submodules are more appropriate.

For example, codecs that include Viterbi and Turbo encoding/decoding functions may consume significant processing resources on a software programmable codec engine, especially when the data bit rate is high (typically more than 100 Mbps). However, these features do not really require software programmability because the differences between the standards are small. Therefore, hardware acceleration using the reconfigurable codec solution to achieve these functions makes more sense than using a software programmable solution. The same is true for channel filtering.

Software radios therefore cannot be entirely software programmable solutions. In fact, the RF front end of the SDR will be a mix of programmability and reconfigurability under software control, with embedded microcontrollers, digital signal processors, vector processors, and hardware accelerators all available.

With the transition of analog-to-digital and digital-to-analog conversions to intermediate-frequency circuits, SDR may also affect the future division of multi-mode, multi-channel RF transceivers. The channel filtering, modem, and codec functions may either be moved to the host's baseband chip or to a separate connected modem engine. This not only reduces the number of chips, but also allows the rapid transition of the modem and baseband functions from one CMOS process technology to another, resulting in rapid cost reductions. At the same time, RF front-ends and power amplifiers can continue to use technologies that provide suitable performance. For 2G, 2.5G and 3G mobile transceivers, BiCMOS or III-V processes may continue to be used for some time to come, although some low-end applications are already migrating to RFCMOS.

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