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(1) Structures supported by all synthesis tools: always, assign, begin, end, case, wire, tri, auply0, supply1, reg, integer, default, for, function, and, nand, or, nor, xor, xnor ,buf,not, bufif0,bufif1,notif0,notif1,if,inout,input,instantitation,module,negedge,posedge,operators,output,parameter.
(2) Structures not supported by all synthesis tools: time, defparam, $finish, fork, join, initial, delays, UDP, wait.
(3) Some tools support structures that are not supported by some tools: casex, casez, wand, triand, wor, trior, real, disable, forever, arrays, memories, repeat, task, while.
The principle of establishing a synthesizable model To ensure the synthesizing of Verilog HDL assignment statements, the following points should be noted during modeling:
(1) Do not use initial.
(2) Do not use #10.
(3) Do not use loop statements with indefinite number of loops, such as forever and while.
(4) Do not use user-defined primitives (UDP components).
(5) Try to use synchronous design circuit.
(6) Unless it is the design of the critical path, the method of describing the design by using the gate-level component is generally not used. It is recommended to adopt the behavioral statement to complete the design.
(7) Use the always process block to describe the combinational logic. List all the input signals in the sensitive signal list.
(8) All internal registers should be able to be reset. When using an FPGA to implement the design, the device's global reset terminal should be used as the system's total reset.
(9) Non-blocking assignment methods should be used as far as possible to describe and model temporal logic. Combinations of logic description and modeling, either with block assignments or non-blocking assignments. But in the same process block, it is best not to use both block assignments and non-blocking assignments.
(10) The same variable cannot be assigned to more than one always process block. You cannot use both blocking and non-blocking assignments for the same assignment object.
(11) If you do not plan to derive a variable as a latch, you must explicitly assign the variable to all conditional branches of an if statement or case statement.
(12) Avoid using mixed rising and falling edge triggers.
(13) The assignment of the same variable cannot be controlled by multiple clocks or by two different clock conditions (or different clock edges).
(14) Avoid using x or z values ​​in branch terms of case statements.
1, initial
Can only be used in the test bench, can not be integrated. (When I use ISE 9.1 synthesis, some simple initials can also be synthesized, I don't know why)
2, events
The event is more useful when synchronizing the test bench and cannot be synthesized.
3, real
Does not support synthesis of real data types.
4, time
Does not support integration of time data types.
5, force and release
Does not support the combination of force and release.
6, assign and deassign
Does not support the reg data type assignment or eliminate synthesizing support for wire data type assignment or eliminate.
7, fork join
Can not be integrated, you can use non-block statements to achieve the same effect.
8, primitives
Supporting the synthesis of gate-level primitives does not support the synthesis of non-gate-level primitives.
9, table
Does not support the synthesis of UDP and table.
10. Sensitive list with posedge and negedge
Such as: always @ (posedge clk or negedge clk) begin ... end
This always block is not synthesizable.
11. The same reg variable is driven by multiple always blocks. 12. Delay The time delay starting with # can't be integrated into the hardware circuit delay. The synthesis tool will ignore all the delay codes, but it will not report errors.
For example: a=#10 b;
Here #10 is the delay for simulation, which is ignored by synthesis tools. In other words, in the synthesis, the equation is equivalent to a=b;
13. Comparison with X and Z Some people may like to compare data with X (or Z) in a conditional expression. They don't know that this is not synthesizable, and the synthesis tool will also ignore it. So make sure the signal has only two states: 0 or 1.
Such as:
1 module synthesis_compare_xz (a,b);
2 output a;
3 input b;
4 reg a;
5
6 always @ (b)
7 begin
8 if ((b == 1'bz) || (b == 1'bx)) begin
9 a = 1;
10 end else begin
11 a = 0;
12 end
13 end
14
15 endmodule
Talk to here today, follow-up will be updated, come on, everyone!