From the microcontroller to ARM, the main need to learn ARM architecture, ARM compared to the microcontroller has some peripherals and bus. In the case of just streaking, if you are familiar with the ARM architecture, then I think there will be no difference between using any ARM architecture chip and using the microcontroller. The reason why the ARM architecture is more complex is of course to run faster and better support system-on-chip, so to a certain extent, if the on-chip system is not well understood, then the understanding of ARM architecture will not be so deep. General purpose register R13 is usually used as a stack pointer. When entering the exception mode, the register to be used can be saved in the stack pointed to by R13. When exiting the abnormal blowing program, the register value stored in the stack pointed to by R13 is popped up. R14 is also called the Link Register (LR), which is the PC's return value. R15 is also recorded as a PC. The ARM instructions are word-aligned and the 0th and 1st bits of the PC's value are always 0. That is 32-bit alignment. For the Cortex-M3, there is a register bank with R0-R15. Where R13 acts as a stack pointer SP. There are two SPs, R13 (MSP) and R13 (PSP), the main stack pointer (MSP) and the process stack pointer (PSP), but only one can be seen at the same time. This is called "banked." "register. These registers are 32-bit. ARM's various modes ARM has the following 7 modes: User mode (user,usr) Mode of normal program execution Fast Interrupt Mode (FIQ,fiq) for high-speed data transmission and channel processing External interrupt mode (IRQ, irq) for normal interrupt handling Supervisor (svc) A protection mode used by the operating system Data Abort Mode (Abort, abt) for Virtual Storage and Storage Protection Undefined (und defined) mode is used to support coprocessors via software guidelines System mode (System, sys) is used to run privileged operating system tasks In addition to the user mode, they are called privileged modes. In privileged modes, except for the system mode, they are called exception modes, ie exception mode. My understanding of the word "abnormality" at first was somewhat biased. I think the abnormal pattern is that this system has made a mistake, but it is not. The meaning of the exception mode is an exception, meaning "when this mode happens, it doesn't say...", for example, an external interrupt will also enter the abnormal mode, but at this time the system is running perfectly. Among them SVC is used in the boot file BOOT program that the system just started, must be SVC before jumping to kernel, SVC has the highest authority, can operate on any register. In bare metal programs we sometimes stay in SVC mode. When it comes to user mode or system mode, the following is my guess, such as entering the linux kernel will be set to sys mode, such as task scheduling, etc. will be in sys mode, and the implementation of user-written applications, the system is In usr mode. The above guesses need to find evidence verification in linux. Among them, FIQ and IRQ are interrupt modes. When an interrupt occurs, it will enter FIQ mode or IRQ mode. As for which mode is entered, it is set by the developer. In theory, the response speed of the FIQ mode is faster than that of the IRQ mode. The abt mode usually occurs when the access address is not aligned. At this time, it will jump to the interrupt vector address to which abt belongs. Und mode should be found after the instruction to find the instruction can not be used, at this point will jump to abt belongs to the interrupt vector address. The above two modes should be the BUG will enter the development process, but also a debugging tool, these errors should be eliminated before the release of the version (I guess = =). Startup file This part only needs to understand the relevant role of the coprocessor CP15 and the ARM or THUMB compilation. Look at the online routines and explanations should not be difficult to understand. We can do anything in the startup file, but usually we can do this: change the size of the program to sort the end, close the watchdog, mask the interrupt, set the clock, set the program from SLEEP or IDLE startup, initialize the SDRAM, set each The mode pointed to by the stack, set the interrupt vector table, determine whether to boot from NOR or NAND FLASH, copy the file to SDRAM, run Main. The above also explains why it is necessary to write an assembly file to start the file, set the SP pointer in each mode, and initiate the jump of the interrupt vector (more interrupts are set for the ARM). Only the assembly language is appropriate. Even in the SOC (system-on-a-chip) each task has its own stack, so the part of the program that changes the stack pointer is also done in the assembly. In short, understanding the startup file is a very good entry point. The basic concept of MMU related address Regarding the MMU, because of the different physical addresses and inconsistencies of various storage devices, it is necessary to place the addresses on a reasonable continuous virtual address, so the MMU appears. The MMU places different addresses in suitable virtual addresses for scheduling. For example, to run LINUX must have MMU support. There are three types of addresses in ARM920T: Virtual Address (VA), Transformed Virtual Address (MVA), Physical Address (PA). Here is an example of what an address does when an instruction is requested: 1. Instruction VA (IVA) issued by ARM920T 2. It is converted into the instruction MVA (IMVA) by the ProcID (number of the process space block where the current process is located). The instruction CACHE (ICACHE) and the MMU see the IMVA. 3. If the protection module on the IMMU confirms that IMVA will not be interrupted and the IMVA tag is also in ICACHE, the instruction data will be read out and returned to the ARM920T core. 4. If the IMVA tag is not in ICACHE, the IMMU will generate a command PA (IPA). The address will give the AMBA bus interface to get external data. So how is VA converted from PID to MVA? This is about 13 in FC15, FCSE PID register R13 is the fast context switch extension process identifier. This register is reset to zero. Reading R13 will get the FCSE PID value. Writing R13 updates the FCSE PID value to [31:25]. Bits [24:0] should be zero. How to use FCSE PID: The addresses issued by the 920T kernel are all in the range of 0-32 MB. The reverse-order space of 4 GB is divided into 1238 process space blocks, and the size of each process space block is 32 MB. Each process space block can contain one process. The system actually uses the virtual address space of the processes in the process space block numbered from 0 to 127 of the 128 process space blocks (I*0x02000000) to (I*0x02000000+0x01FFFFFF). So VA is usually high when all 7 bits are 0. MVA = VA | (PID << 25) When the VA high 7 bits are not 0, MVA = VA, this VA is a virtual address used by the process to access data and instructions in other processes. Note that the process identifier being accessed cannot be 0 at this time. Note: When the FCSE_PID is 0, that is, the current reset, the current 920T and CACHES and MMU is a plane mapping relationship (very clever:)). What is TLB? TLB translate look-aside buffer, fast table is to store several commonly used page tables, in order to improve the speed of the system. Before updating the page table, it must be invalidated. The register for its operation is R8. R8 is a write-only register, and reading it will cause incalculable consequences. AP assignment table: The DOMAIN assignment is in C3, 32bit total 16 domains, each domain is divided into two bits, these two bits control the current domain permissions. The above four bits are for selecting one of 0-15 domains. About C, B assignments: The above is about two kinds of write cache, write and write back. The write back method refers to that when the CPU performs a write operation, the written data is only written into the cache, and is not written into the main memory. Only when it needs to be replaced, the cached block that has been modified is written back to the main memory. Write-through means that the CPU must write data to the cache and main memory at the same time when performing a write operation. Clock and bus concept FCLK, HCLK, andPCLK FCLK is used byARM920T. HCLK is used for the AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface, ADC, UART, GPIO, RTC and SPI. What is AHB/APB? The InternalAdvanced Microcontroller Bus Architecture (AMBA) is a bus standard and both of the following are in compliance with this standard. AHB (Advanced High Performance Bus) is mainly used for system high-performance, high-speed rate module communication. APB (Advanced Peripheral Bus) is mainly used for communication between slow on-chip peripherals and the ARM core. The AHB Private Peripheral Bus is used only for the AHB peripherals inside the CM3. These are: NVIC, FPB, DWT and ITM. The APB Private Peripheral Bus is used both for APB devices inside the CM3 and for external devices (the “external†here is for the kernel). CM3 allows device manufacturers to add some on-chip APB peripherals to the APB private bus, which are accessed through the APB interface. Four power consumption modes: NORMAL, SLOW, IDLE, SLEEP First configure the main PLL MPLL for the CPU. The PLL is unstable during a power-on reset, so Fin skips MP11 directly to FCLK before PLLCON is configured by software, so configuring PLLCON is also fine. Even under normal operation, the MPLLCON can be configured. After the configuration, the CLKs of the internal modules can be normally supplied after waiting for the PLL lock-time. 220V To 110V Transformer,220 To 110 Converter,220 To 110 Voltage Converter,110V Transformer zhejiang ttn electric co.,ltd , https://www.ttnpower.com