The switch used for the normal button is a mechanical elastic switch. When the mechanical contact is opened and closed, due to the elastic action of the mechanical contact, a push button switch does not immediately turn on when closed, and also when disconnected. Will not be disconnected at once. Therefore, there are a series of jitters at the moment of closing and breaking, and the measure for not generating this phenomenon is the button debounce. The length of the jitter time jitter time is determined by the mechanical characteristics of the button, typically 5ms to 10ms. This is a very important time parameter. In many cases, the length of the button to be used for stable closing time is determined by the operator's button action, usually from a few seconds to a few seconds. Key jitter causes a key to be misread multiple times. To ensure that the FPGA only performs one processing of the key closure, the key jitter must be removed. The state of the key is read when the key is closed, and it must be determined that the key release is stable before processing. Figure 1 Key Jitter The method of implementing debounce in the FPGA There are many ways to implement button debounce in the FPGA, but the simplest method is to use the shift register method for debounce. Because the shift register method does not need to divide the clock, and does not need complicated operations such as delay, the detection of the edge of the button can be realized. Assume that the key value = 1 when not pressed. 1. When no key is pressed, the shift register samp[7:0] always acquires a high level, that is, samp[7:0]=8'b1111_1111; 2. When the key is pressed, samp[7:0] will acquire low level, and the data change mode is samp[7:0]=8'b1111_1110-->8'b1111_1100-->8'b1111_1000-- > ........——>8'b0000_0000;samp[7:0]=8'b1111_1110 is the falling edge of the button. 3. When the button is released, samp[7:0] will be reacquired to the high level, and the data change mode is samp[7:0]=8'b0000_0001-->8'b0000_0011--> ..... ...-->8'b1111_1111; when samp[7:0]=8'b0111_1111, it is the rising edge of the button. Figure 2 shift register debounce schematic Refer to the Verilog code Module EdgeDetect( Reg[7:0] samp; / / shift register capture button key value / / Generate rising edge information / / Generate falling edge information European Socket Connector,Straight Needle European Socket Connector,Waterproof European Socket Connector,Vertical Straight European Socket Connector Shenzhen Jinyicheng Electronci Technology Co.,Ltd. , https://www.jycconnector.com
/ / Module name: EdgeDetect, edge detection
//button: button, high level when no key is pressed //clk: 10M clock
//rst: reset button, active low
//rise: detected rising edge, active high, width 1 clk
//fall: detected falling edge, active high, width 1 clk
Input clk,
Input rst,
Input button,
Output reg rise,
Output reg fall
);
/ / Shift register capture button information
Always@(posedge clk or negedge rst)
Begin
If(!rst)
Samp<=8'b1111_1111;
Else
Samp<={samp[7:1],button};
End
Always@(posedge clk or negedge rst)
Begin
If(!rst)
Rise<=1'b0;
Else if(samp==8'b1111_1110)
Rise<=1'b1;
Else
Rise<=1'b0;
End
Always@(posedge clk or negedge rst)
Begin
If(!rst)
Fall<=1'b0;
Else if(samp==8'b0111_1111)
Fall<=1'b1;
Else
Fall<=1'b0;
End