DCM: Digital Clock Manager digital clock management, about the role of DCM: As the name suggests, the role of DCM is to manage, control the dedicated module of the clock. Can complete the crossover, multiplier, goskew, phase shift and other functions. The DCM consists of four separate functional units: 1, Delay-Locked Loop (DLL); 2, Digital Frequency Synthesizer (DFS); 3, Phase Shift (PS); 4, Status Logic (SL); About the role and difference of external feedback & internal feedback: The purpose of the feedback is similar to the principle of the phase-locked loop, in order to ensure that the clock phase adjusted by the DCM is aligned with the input (ie, eliminating skew due to DCM clock adjustment). The internal feedback is to ensure that the internal clock is aligned with the clock on the IO PAD of the input chip. The external feedback is to ensure that the phase of the output to the external clock (such as the SRAM) is aligned with the phase of the clock on the IO PAD of the input chip. (Internal feedback is not connected by yourself) The IBUFG and BUFG inside the FPGA will bring delay to the input clock. After DCM, the output of clk0 can be utilized (due to feedback). At this time, the output phase can be consistent with the input phase on the IPAD, which is equivalent to zero delay BUF. Useful in high speed design. The two implementations of feedback: one is CLK0 feedback (ie, the same frequency of CLKIN is used as the feedback signal), and the other is CLK2X feedback (ie, the double frequency of CLKIN is used as the feedback signal). Also, if you only use CLKFX & CLKFX180, you can not use feedback. See Figures 2 and 3 for details: The DLL in DCM has two working modes: High Frequency & Low Frequency Mode. Low frequency mode 24MHz~180MHz, high frequency mode 48MHz~360MHz (different devices may be different). The reset RST of the DCM is active high (this is different from the low reset that we normally touch), and the duration of the reset signal is required to be at least three times the input clock period during the simulation. The frequency synthesized output CLKFX = M / D & TImes; CLKIN (M is determined by CLK_MULTIPLY, D is determined by CLK_DIVIDE). The phase shift is divided into three modes: one: NONE; two: fixed phase shift; three: variable phase shift; The two main applications are: one: system clock synchronization; two: source synchronization: The default is the system clock synchronization mode, which automatically adds a small delay to capture data with zero hold time. Patch Panel,48 ports patch panel,half U patch panel,patch panel 24 port NINGBO UONICORE ELECTRONICS CO., LTD , https://www.uonicore.com
The internal clock is used internally by the FPGA, and the external is the clock that needs to be sent to the outside at the same time according to the design requirements.
In high-frequency mode, the multiplier disables the output pin clk2X&clk2x180, and the output of the four-phase shift register, CLK90 & CLK270, is also disabled. If the division factor is not an integer, the duty cycle of the output clock is not 50%.
If only CLKFX is used as the output, the input clock can be 1MHz~210MHz, but the output should be at least 24MHz.
Two settings:
One: Fill in the value of the output clock CLKFX to be output, and the tool automatically calculates the value of M&D.
Two: Set the M&D value according to the desired output.
NONE (default): no phase shift input & output in phase, equivalent to fixed phase shift set to 0;
Fixed phase shift: the phase value of the output relative to the input delay is fixed (phase shift value is also T/256, range: -128~128);
Variable phase shift: If the value of the phase shift enable pin PSEN is high (PSEN can only be one PSCLK cycle at a time), the output CLK0 starts to phase shift, and it is judged whether to increase or decrease according to the value of PSINCDEC, CLK0 will move one. Phase (relative to the phase of CLKIN, the value of the movement is T/256, T is the period of CLKIN), and PSDONE will generate a pulse to indicate that the phase shift is completed. Only when the output of LOCKED is high indicates that it is locked, the output clock effective. The phase shift range is -64 to 64 (ie -π/4 to π/4), so theoretically a clock signal that is arbitrarily different from CLKIN can be obtained, which may be useful in generating signal delays, some specific operations and requirements. You can refer to the user manual.
From the perspective of the delay period, it can also be divided into:
One: 1/2 period phase shift (CLK0, CLK180); two: 1/4 period phase shift (CLK0, CLK90, CLK180, CLK270);
Three: fixed phase shift (T/256); four: dynamic variable phase shift (T/256);
The so-called system clock synchronization (that is, the common clock system): the driving clock in the same data path is the same clock resource.
The so-called source synchronization system: the data & source synchronous clock signal is synchronously transmitted, ensuring that the flight time of two clock signals (time of flight including propagation delay & time of rising edge change) is consistent, theoretically the highest frequency of the system clock Without any restrictions, it is a general method of high-speed data transmission.
The clock & data of the source synchronous system is synchronized. When sampling, the clock is generally taken to the middle of the data, while the setup & hold time is satisfied.