In a factory environment, 4mA to 20mA analog current loops are common. Although the basic signal modulation is the same in all applications, the bandwidth requirements are quite different. Factory control systems may require hundreds of Hz loop bandwidth (from position and displacement sensors), while typical process control systems require only a few Hz update rates and typically support HART (addressable remote sensor high speed channel). The HART protocol allows bidirectional 1.2/2.2 kHz FSK (Frequency Shift Keying) modulated digital communications in a traditional analog 4mA to 20mA current loop. Designing a 4mA to 20mA input that satisfies both conditions can be difficult. The circuit diagram in Figure 1 is a traditional deployment method that supports HART analog inputs. Figure 1: Inputs that integrate passive filters and support HART. In the figure, R1 and RSENSE form a 250Ω system termination impedance. The HART FSK signal is AC coupled from there to the HART modem. The 4mA to 20mA analog signal is converted to a 0.4V to 2V signal by a precision 100Ω RSENSE resistor. The analog low-pass filter then attenuates the HART FSK component of the analog signal and then inputs it to the ADC. The second-order low-pass analog filter has a bandwidth of 25 Hz and a roll-off of -40 dB/decade. The circuit complies with the HART specification and attenuates the HART FSK signal to more than -60dB below 4mA to 20mA full scale, ensuring HART FSK communication input disturbances do not exceed 0.1%. On the other hand, the analog low-pass filter takes approximately 70 ms to establish within 0.1% after a full-scale transition at the input of the system. This long settling time and low bandwidth performance is not suitable for systems that require high speed operation and do not require HART communication. It is indeed possible to bypass the analog filter, but requires additional analog circuitry such as switches or multiplexers. Figure 2 shows an alternative to the HART-enabled analog input. Figure 2: Flexible bandwidth input with HART support. Similar to the previous circuit, the HART FSK signal is ac-coupled to a 250Ω input impedance, while the 4mA to 20mA signal is converted to a 0.4V to 2V signal by a 100Ω precision RSENSE resistor. In this circuit, however, a mild low-pass filter limits the signal bandwidth to around 27 kHz to provide immunity and electromagnetic compatibility (EMC) to the system. After the full-scale transition of the system input, the filter is set to 0.1% in 40μs. The signal is passed to a Σ-Δ ADC with a built-in digital filter, such as the Analog Devices AD7173. The digital filter can be programmed to be set to a slower operating speed mode and an optimal HART FSK signal rejection mode, or to a fast operating mode when fast analog input is required. The AD7173 supports multiple modes of operation. One of these modes is suitable for suppressing HART FSK signals, setting the notch frequency of the SINC3 filter to 400 Hz, or providing deep filter notch at lower HART FSK frequencies (1.2 kHz) and at higher frequencies ( A fractional frequency that provides significant attenuation at 2.2 kHz). The curve in Figure 3 shows the frequency response of the digital filter and its comparison to the analog filter of Figure 1. Figure 3: Inputs that integrate passive filters and support HART. Unfortunately, the real situation is far from simple. When a complete message is transmitted via HART, the HART FSK modulated signal spectrum contains not only the electrical energy at the fundamental frequency modulation frequency, but also the frequency components between, below and above the 1.2 kHz and 2.2 kHz carriers. Figure 4 shows the typical spectrum of the HART FSK message at the ADC input and the spectrum as attenuated by the SINC3 filter with a 400Hz notch. In this example, the host sends a HART command of 3, and the slave responds to the command. Figure 4: HART message spectrum. As can be seen from Figure 4, a portion of the HART message (especially at lower frequencies) can still appear in the A/D output data. This means that the digital filter settings can be easily changed to achieve the right balance between HART FSK sample input speed and rejection. Figure 5 shows the system performance. The measured values ​​are expressed as a percentage error over the 4 mA to 20 mA full-scale range, while comparing the system speeds of the analog filter (Figure 1) and the SINC3 digital filter (Figure 2). Figure 5: SINC3 filter and analog filter. The analog filter is fixed in hardware and has a fixed settling time. For fast-changing analog signals at the system input, the analog filter output error is determined by its slow settling time. For example, if the system input changes the full scale every 40ms, the filter output will not be built to within 1% of the correct value. For slower input signals, the analog filter output error is determined by its ability to reject the low frequency components of the HART FSK signal. For a typical HART Command 3 message, the error measurement is approximately 4 mA to 0.09% of 20 mA full scale. In addition, the settling time of the digital SINC3 filter is a user-set parameter, and the filter output error is determined by the filter settings corresponding to the HART FSK modulation. For example, a 400 Hz notch SINC3 filter corresponds to a 7.5 ms settling time. When HART command 3 is transmitted, the measured disturbance on A/D is less than 4 mA to 0.4% of 20 mA full scale. In systems with four analog inputs, the SINC3 filter switches sequentially between channels. The same 400Hz notch SIN3 filter now requires 4&TImes; 7.5 = 30ms to scan all four channels. This is why the curve of the four-channel system shows an error of about 0.4% at 30 ms. For more accurate 4 mA to 20 mA inputs, the SINC3 filter can be set to a 30 ms settling time, which corresponds to a 100 Hz notch and suppresses the HART signal to less than 0.1% of full scale. If speed is more important, the SINC3 filter with a 6ms settling time (approximately 500Hz notch) can still suppress HART communication signals below 0.5% of the 4mA to 20mA input. In addition, if only speed is required and no HART communication is required, the AD7173 mentioned above can achieve a sampling rate of 3 ksps with a settling time of 161 μs per channel. Traditional analog low-pass filters are easier to understand, and in some cases, a few additional components per channel can achieve better analog input performance in multi-channel systems. On the other hand, the integrated digital SINC filter of the Σ-Δ ADC is extremely flexible, and this flexibility is available all the way to end system users. Digital solutions require less hardware and, if properly configured, are superior to analog solutions in single-channel systems in HART FSK signal filtering performance, and have near or better performance than up to four-channel systems. . Dongguan City Yuanyue Electronics Co.Ltd , https://www.yuanyueconnector.com
