In order to improve the accuracy of the instrumentation system, the performance of the digital-to-analog converter has exceeded 16 bits, and it has been necessary to use a cumbersome, expensive, slow-speed Kelvin-Varley voltage divider to achieve this level of performance. However, as time goes by, markets and technologies continue to evolve, and the definition of precision digital-to-analog converters has changed. The development of semiconductor processing technology, DAC design and calibration technology has made it possible to have high linearity digital-to-analog converters. This converter not only has good stability, short settling time, but also provides 20-bit performance better than 1ppm. These small ICs guarantee performance specifications that require no calibration and are easy to use. The range of applications for 1ppm DACs ranges from gradient coil control in medical MRI systems to precision sources and positioning in mass spectrometry, test and measurement applications. Performance The circuit shown in Figure 1 provides 1 ppm performance. The key specifications are integral nonlinearity, differential nonlinearity, and 0.1 Hz to 10 Hz peak-to-peak noise. In Figure 1, U1 is a 20-bit DAC with a 1ppm linearity specification. U2 is a precision dual-channel amplifier that acts as a drive-detect buffer for the DAC reference input. U3 is a precision output buffer that is used to drive the load. Its key requirements are similar to the reference buffer, which includes low noise, low offset voltage, low drift, and low input bias current. Although there are less than 1ppm of precision components available, building a 1ppm system is not an easy task and should not be taken lightly. The main sources of error in 1ppm precision circuits are noise, temperature drift, and thermoelectric voltage. *noise To achieve a true 1ppm system, noise must be minimized. U1 has a noise spectral density of 7.5 nV/vHz. U2 and U3 have a nominal noise density of 2.8 nV/vHz, which is much lower than the noise contribution of the DAC. Wideband noise can be removed by filtering, but low frequency noise (1/f) in the range of 0.1 Hz to 10 Hz cannot be filtered out. The most effective way to minimize this noise is device optimization and selection. U1 produces 0.6μV pp noise at 0.1Hz to 10Hz bandwidth, well below 1LSB (1LSB = 19μV for ±10V output). The design target value of 1/f noise in the system should be about 0.1LSB or about 2μV. The three amplifiers in the signal chain generate a total of approximately 0.2 μV pp of noise at the output of the circuit. Adding 0.6μV pp noise from U1, the total 1/f noise is expected to be 0.8μV pp. *temperature drift Temperature drift is another major source of error in precision circuits. The temperature coefficient of U1 is 0.05 ppm/°C. The drift coefficient of U2 is 0.6μV/°C, which means that a drift of 0.03ppm / °C is introduced into the circuit as a whole. At the same time, U3 contributes an output drift of 0.03ppm/°C, so that the sum of the three is 0.11 ppm/°C. For regulation and gain circuits, it is recommended to use a low drift, thermally matched resistor network such as Vishay's 300144Z and 300145Z. *Thermal voltage The thermoelectric voltage is the result of the Seebeck effect: a temperature-dependent voltage is generated at the junction of the heterogeneous metal. The resulting voltage is between 0.2 μV/°C (copper-copper junction) to 1 mV/°C (copper-copper oxide junction). The thermoelectric voltage appears as a low frequency drift similar to 1/f noise. Keep all connections clean, eliminate oxides, and shield the circuit from airflow, which can significantly reduce the thermoelectric voltage. The figure below shows the difference in voltage drift between open and shielded circuits. Long-term stability of voltage drift and time in open and closed systems Although the precision analog IC is very stable, it does undergo long-term aging changes. The long-term stability of the DAC is generally better than 0.1 ppm/1000 hours, but aging does not have cumulative properties, but follows the square root rule. If the aging rate of a device is 1ppm/1000 hours, then 2000 hours aging 2ppm, 3000 hours aging 3ppm, and so on. Generally, for every 25 °C decrease in temperature, the time is extended by a factor of 10; therefore, when the operating temperature is 100 ° C, during the 10,000 hour period (about 60 weeks), the aging is expected to be 0.1 ppm. And so on. During the 10-year period, the aging is expected to be 0.32ppm. Circuit construction and layout In circuits where accuracy is important, careful consideration of the power and ground loop layout helps ensure that rated performance is achieved. When designing the PCB, the design of the analog part and the digital part should be separated and limited to different areas of the board. A large enough (10μF) power supply bypass capacitor must be used in parallel with the 0.1μF capacitor on each supply and as close as possible to the package. These capacitors should have low equivalent series resistance and low equivalent series inductance. If a ferrite bead is connected in series on each power supply line, the high frequency noise passing through the device can be further reduced. Power lines should use as wide a trace as possible to provide a low impedance path and reduce the effects of glitches on the power line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other devices on the board and should never be placed near the reference input or under the package. Avoid crossing digital signals with analog signals, and their traces on opposite sides of the board should be perpendicular to each other to reduce the feedthrough effects of the board. Build a 1ppm analog-to-digital conversion solution A typical modern 1ppm analog-to-digital conversion solution consists of two 16-bit digital-to-analog converters—one main DAC and one auxiliary DAC. The outputs are scaled and combined to produce higher resolution. The main DAC output is added to the attenuated auxiliary DAC output, allowing the auxiliary DAC to fill the resolution gap between the main DAC LSB steps. The combined output needs to be monotonic, but the linearity does not need to be extremely high, because the high performance is achieved by the constant voltage feedback of the precision analog-to-digital converter, which corrects the inherent component errors. Therefore, circuit accuracy is limited by the ADC and is not limited by the DAC. However, due to the constant voltage feedback required and the inevitable loop delay, this solution is slow and the setup time can be as long as several seconds. Although this circuit can achieve 1ppm accuracy, it is difficult to design, it is likely to need to repeat the design multiple times, and the target precision is required by the software engine and precision ADC. In order to guarantee 1ppm accuracy, the ADC needs to be calibrated, because there is no ADC that guarantees 1ppm linearity on the market. The block diagram shown here is only a conceptual demonstration. The real circuit is much more complicated, involving multiple gains, attenuations and The summation level includes many components. Digital circuits are also needed to facilitate the interface between the DAC and the ADC, not to mention the software used for error correction.
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