The appearance of software radio is the third change from hardware to software in radio communication from analog to digital, from fixed to mobile. In a nutshell, SDR is a multi-band, multi-mode, reconfigurable and programmable radio system that is based on a common hardware platform and can provide multiple services through software. The key idea of ​​software radio is to place AD(DA) as close to the antenna as possible and use software to perform as many radio functions as possible. The cellular mobile communication system has been developed to the third generation. When 3G systems enter into commercial operations, they need to solve the compatibility of systems with different standards. On the other hand, the system requires a high degree of flexibility and expands the upgrade capability. The software radio technology is undoubtedly the most Good solution. The use of ASICs (ApplicaTIon Specific Intergrated CIRcuits) and DSP (Digital Singular Processor) chips to build software radio platforms is currently the main method of system design. This method has two outstanding drawbacks: First, system speed can not keep up with high-speed dynamic real-time digital signal processing. The second is that the system has a large volume and high power consumption. These two outstanding defects have restricted the application of software radio in high-speed real-time communications. This paper uses the current Field Programmable Gate Array based SoPC (System on Programmable Chip) technology to build a software radio platform. The ability and speed of digital signal processing have been greatly improved, and the system power consumption has been reduced, the system volume has been reduced, and solutions have been provided for higher-level 3G wireless communication requirements. 1.1 System Design Software Radio makes the radio have more personalized features. It defines multiple frequency bands and multiple modulation waveform interfaces in software. The software radio system includes signal transmission and reception. This article focuses on the reception process. Software Radio's RF (Radio Frequency) part is a multi-beam antenna array that can receive multiple frequency bands, multiple directions of RF signals, and convert the RF frequency to an IF signal. As shown in Figure 1, the system includes Virtex-4FX series FPGA, analog signal input port, synchronous trigger port, external clock source, Flash (load FPGA configuration program), CPLD, SDRAM, PCI interface, LED signal lamp and other parts. Extracting the user's narrowband signal for extraction is performed by a dedicated ADC chip, and the digital down-conversion part is completed by an IP (Intellectual Property) module in the FPGA. Using a dedicated chip for analog-to-digital conversion can improve the stability and reliability of the system; using the IP block to perform digital down-conversion can reduce power consumption and increase the rate. After digital down-conversion, it is demodulated, and the demodulated signal is a bit stream sequence. The bit stream processing part needs to complete the information encryption, decryption, coding and decoding. As shown in Figure 1, this part of the function can be written in Verilog-HDL language DSP processing module, you can also use Matlab FDATool after the design of the automatic generation of Verilog-HDL source code and PowerPC instruction program; this article uses Verilog-HDL to directly write DSP The module approach allows for better control of the hardware processing flow and better signal processing performance. Since the DSP module is embedded in the FPGA, the design can be made more flexible by increasing or decreasing the DSP logic circuit. For example, the 2FSK modulation and demodulation, the FIR filter and the FFT can be packaged into a unit module, and the address-driven PowerPC program can be directly executed. Calling, compared to the DSP-specific processor only calls the multiplier and shift register method can save hundreds of instruction cycles, greatly improving the ability of real-time signal processing, and has broad application prospects in the high-end field. After the bit stream sequence processing is completed, the data can be transferred to the host disk array for storage, and the PowerPC controls the data transmission of the system and the host through the PCI bridge to meet the requirements of future data playback and visual interface. 1.2 ADC Analog to Digital Conversion The software radio requires the ADC and DAC to be as close as possible to the antenna. This requires high ADC sampling rate, sampling accuracy, and dynamic range. The AD9042 is a high-performance, high-speed ADC chip that uses a two-level subarea conversion structure. This design not only guarantees the required conversion accuracy and conversion speed, but also reduces power consumption while also reducing the chip size. The AD9042 system principle is shown in Figure 2. The AD9042 can guarantee a minimum sampling rate of up to 41MHZ, 12bit accuracy, and 80dB spurious free dynamic range. 1.3 DDS Direct Frequency Synthesis Due to the limited processing speed of digital signal processing, it is often difficult to directly perform various types of real-time processing on high-rate digital signals obtained by A/D sampling. In order to resolve this contradiction, it is necessary to use digital down-conversion technology to convert the sampled high-rate signal to a low-rate baseband signal for further signal processing. Digital down conversion technology has been widely used in software radios and various types of digital receivers. Broadband digital down converters are based on the principle of heterodyne receivers, including digital mixing, low-pass filtering, and decimation. After extraction, the baseband sampling signal matched with the signal bandwidth is obtained to achieve the purpose of extracting a narrowband signal from a wide frequency band. The dedicated DDS (Direct DIGItal Synthesizer) IP module provided by Xilinx is used to implement the digital down conversion function. 1.4 CPU Control Unit The Virtex-4 FX family of FPGAs integrates dual 32-bit embedded PowerPCs running at speeds up to 450 MHz. Each processor provides over 700 DhrySTone MIPS performance, which is three times the processor performance in an ordinary FPGA. Two fully integrated UNH-certified 10/100/1000 Ethernet MACs further enhance the performance of the Virtex-4 FX processing platform, thereby increasing the availability of FPGA resources. The system uses PowerPC as the instruction processing and control unit of the system, which can avoid the drawbacks of pure hardware design, poor versatility, and not easily coordinated control. PowerPC is the core component of the SoPC architecture of this system, and it is responsible for two tasks: algorithm implementation and central control. Virtex-4 FX has a large number of multipliers available for internal calls and can fully meet various digital signal processing requirements. PowerPC is connected with the DSP module designed with Verilog-HDL as mentioned above, so that the whole system has the real-time dynamic signal processing capability. PowerPC as a controller's state flow is shown in Figure 3. In modern communications, the carrier signal of the modulator is almost all sinusoidal, and the digital baseband signal changes the sinusoidal carrier frequency through the modulator to generate a frequency shift keying (FSK) signal. The FSK time domain expression is The block diagram of the FSK modulation structure implemented with this system is shown in Fig. 4. The FSK modulation module written in Verilog-HDL language is shorter than the implementation of the traditional software radio. It saves the time of reading the instruction cycle and shortens the total operation time. half. The ModelSim waveform simulation result of FSK modulation is shown in Fig. 5. The improved FPGA-based embedded software radio system can better meet the real-time requirements of signal processing in high-tech fields such as communications, radar and digital television. The use of software radio and SoPC technology has greatly improved the system's dynamic real-time signal processing capabilities. In terms of resource conservation, the system saves more than 30% in power consumption and volume compared to the current conventional systems in terms of chip count savings. 40MHZ clock frequency, 12bit accuracy, 80dB spurious free dynamic range, the system can be applied to Cellular / PCS base station, multi-channel multi-mode receiver, GPS anti-jamming receiver, phased array receiver, spectrum analysis, 3G wireless communication and other fields .
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